1. Field of the Invention
This invention relates to a source electrode-connected type logic circuit (SCFL) employing a field effect transistor, and more particularly to an SCFL for use in a high frequency digital circuit.
2. Description of the Related Art
A buffer circuit for use in a digital circuit which must operate at high frequency, such as a multiplexer for optical communication or a divider for satellite broadcast, has a source coupled FET logic circuit (SCFL) of a LDD (Lightly Doped Drain) structure made of GaAs. The reason why the buffer circuit has the LDD structure is that the structure enhances high frequency characteristics thereof.
The LDD structure, however, makes it difficult to broaden the distance between the gate and drain, thereby reducing the breakdown voltage of the circuit. For example, a circuit of a non-LDD structure has a breakdown voltage of 6-10V or more, whereas a circuit of the LDD structure has a breakdown voltage of approximately 4V. Further, in recent years, power consumption has been required to be reduced.